Datacom and telecom multiplexers and demultiplexers send and receive many high speed serial data streams. This data is traditionally passed through standard Synthesized and Placed and Routed digital cores. To pass the high speed data through the digital core, the data-rate must be dropped significantly. The multiplexing and demultiplexing stages that drop the data rate use additional power and increase the latency of the data through the design. Designs that use a standard place and route digital core can be non-optimized and inefficient with large layout areas and high parasitics when compared to custom schematic based design.
The above-described deficiencies of datacom and telecom multiplexers and demultiplexers are merely intended to provide an overview of some problems of current technology, and are not intended to be exhaustive. Other problems with the state of the art, and corresponding benefits of some of the various non-limiting implementations described herein may become further apparent upon review of the following detailed description.